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T6K11
TOSHIBA CMOS DIGITAL INTEGRATED CIRCUIT SILICON MONOLITHIC
T6K11
DOT MATRIX LCD DRIVER
The T6K11 driver is designed for use in small to medium-sized dot matrix LCD panels. This driver can be interfaced to the MPU via a 4 / 8-bit (68 / 80-series) or a serial interface, and is operated asynchronously with the MPU. Since the T6K11 contains an CR circuit clock driver, it can generate the timing signals required for the LCD. The display data can be stored in the built-in display RAM, whose cells each correspond to each dot on the dot-matrix LCD. The display data written to the RAM corresponds one for one to the LCD drive signals output by the device. Since the T6K11 has 160 outputs for the LCD drive (segment) signals that constitute display data and 65 outputs for the LCD drive (common) signals that constitute scanning signals, this single device allows you to drive an LCD panel comprised of up to 160 x 65 dots with a minimum of power requirement. To minimize its power consumption, the T6K11 has a display change mode (power save mode) in which only a 160 x 1-dot icon can be displayed. What's more, it has various built-in analog circuits such as a D / A converter for the LCD drive power supply, a step-up circuit (x2 to x5), and a contrast control (electronic VR) circuit. All these circuits enable the LCD panel to be driven with a single power supply. This product is under development; hence, specifications may change without notice. When you use this product, please refer to the latest technical datasheet.
000707EBE1
* TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such TOSHIBA products could cause loss of human life, bodily injury or damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most recent TOSHIBA products specifications. Also, please keep in mind the precautions and conditions set forth in the "Handling Guide for Semiconductor Devices," or "TOSHIBA Semiconductor Reliability Handbook" etc.. * The TOSHIBA products listed in this document are intended for usage in general electronics applications (computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). These TOSHIBA products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or bodily injury ("Unintended Usage"). Unintended Usage include atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, medical instruments, all types of safety devices, etc.. Unintended Usage of TOSHIBA products listed in this document shall be made at the customer's own risk. * Polyimide base film is hard and thin. Be careful not to injure yourself on the film or to scratch any other parts with the film. Try to design and manufacture products so that there is no chance of users touching the film after assembly, or if they do , that there is no chance of them injuring themselves. When cutting out the film, try to ensure that the film shavings do not cause accidents. After use, treat the leftover film and reel spacers as industrial waste. * Light striking a semiconductor device generates electromotive force due to photoelectric effects. In some cases this can cause the device to malfunction. This is especially true for devices in which the surface (back), or side of the chip is exposed. When designing circuits, make sure that devices are protected against incident light from external sources. Exposure to light both during regular operation and during inspection must be taken into account. * The products described in this document are subject to the foreign exchange and foreign trade laws. * The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by TOSHIBA CORPORATION for any infringements of intellectual property or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any intellectual property or other rights of TOSHIBA CORPORATION or others. * The information contained herein is subject to change without notice.
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Features
l Display RAM l LCD drive outputs l RAM data direct display l Display duty cycle : 160 (64 + 1) = 10,400 bits : 160 segment outputs 65 common outputs (including one common output for icon) : Turned on when bit data in RAM = 1 Turned off when bit data in RAM = 0 : 1/2 duty during power save mode 1/35, 1/49, 1/57, or 1/65 duty during normal mode (Duty cycles in normal mode are set in software by the MPU.) : Normal mode ............. Full display Power save mode ....... Icon display Standby mode ............ Clock stop (all internal circuits turned off) : 8-bit (68 / 80 series) parallel or serial interface : Built-in CR oscillator (resistor and capacitor completely built-in), external clock input acceptable : D/A converter for LCD drive power supply (temperature derating = 0.20% / C), step-up circuit (x2 to x5), contrast control circuit : AVDD (used for analog) = DVDD to 5.5 V DVDD (used for digital) = 1.8 to 3.3 V : VCC = 16.5 V (max) : ISS = 103 A (typ.) Conditions: AVDD = DVDD = 3.0 V, step-up circuit used (x4 mode), LCD nonloaded, Ta = 25C, display data = all "checker pattern," no data access from MPU :
Product T6K11(XXX, XXX) JBT6K11-AS Package TCP (Tape carrier package) Gold Bump Chip
l Display modes
l MPU l Oscillator l Power supply circuits l Operating voltages l LCD drive voltage l CMOS process l Low power consumption
l Package
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Block Diagram
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Pin Assignment
Note: The above TCP pin assignment is shown for reference purposes only.
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Pad Specification
Item Chip size (1) Chip tip coordinates (2) (3) (4) Bump pitch Bump height Size 10360 x 2550 -5180 -5180 5180 5180 , , , , 60 14 4 -1275 1275 1275 -1275 mm mm mm Unit mm
Item Input pin Output pin Fuse pin Test pin
Number of pins 116 pin (including dummy pins) 226 pin (including dummy pins) 33 pin (including dummy pins) 19 pin (Note 1) (Note 1)
(Note 1): Fuse (No.117 to 149) and Test (No.376 to 394) are LSI test pins, leave these pins open.
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Pad Layout
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Pad Coordinates
(Unit: m) No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 Name DVDD /STB DVSS /CS1 CS2 DVDD /RST DUMMY1 RS DVSS /WR /RD DVDD DB0 DB1 DB2 DB3 DB4 DB5 DB6 DB7 DUMMY2 DVDD DVDD DVDD DVDD DVDD DUMMY3 DVSS DVSS DVSS DVSS DVSS CL DVDD CLS DVSS DUMMY4 AVSS AVSS X -4753 -4672 -4608 -4544 -4480 -4416 -4352 -4288 -4224 -4160 -4096 -4032 -3968 -3904 -3840 -3776 -3712 -3648 -3584 -3520 -3456 -3392 -3328 -3264 -3200 -3136 -3072 -3008 -2944 -2880 -2816 -2752 -2688 -2624 -2560 -2496 -2432 -2368 -2304 -2240 Y -1090 -1090 -1090 -1090 -1090 -1090 -1090 -1090 -1090 -1090 -1090 -1090 -1090 -1090 -1090 -1090 -1090 -1090 -1090 -1090 -1090 -1090 -1090 -1090 -1090 -1090 -1090 -1090 -1090 -1090 -1090 -1090 -1090 -1090 -1090 -1090 -1090 -1090 -1090 -1090 No. 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 Name AVSS AVSS DUMMY5 AVDD AVDD AVDD AVDD DUMMY6 C1A C1A C1B C1B VOUT1 VOUT1 C2A C2A C2B C2B VOUT2 VOUT2 C3A C3A C3B C3B VOUT3 VOUT3 C4A C4A C4B C4B VOUT4 VOUT4 VCC VCC VCC VCC DUMMY7 AVSS AVSS DUMMY8 X -2176 -2112 -2048 -1984 -1920 -1856 -1792 -1728 -1664 -1600 -1536 -1472 -1408 -1344 -1280 -1216 -1152 -1088 -1024 -960 -896 -832 -768 -704 -640 -576 -512 -448 -384 -320 -256 -192 -128 -64 0 64 128 192 256 320 Y -1090 -1090 -1090 -1090 -1090 -1090 -1090 -1090 -1090 -1090 -1090 -1090 -1090 -1090 -1090 -1090 -1090 -1090 -1090 -1090 -1090 -1090 -1090 -1090 -1090 -1090 -1090 -1090 -1090 -1090 -1090 -1090 -1090 -1090 -1090 -1090 -1090 -1090 -1090 -1090 No. 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 Name VLC0 VLC0 VLC1 VLC1 VLC2 VLC2 DUMMY9 VLC3 VLC3 VLC4 VLC4 VLC5 VLC5 DUMMY10 AVSS DUMMY11 DVSS 68/80 DVDD P/S DVSS X 384 448 512 576 640 704 768 832 896 960 1024 1088 1152 1216 1280 1344 1408 1472 1536 1600 1664 1728 1792 1856 1920 1984 2048 2112 2176 2240 2304 2368 2432 2496 2560 2624 2688 2752 2816 2880 Y -1090 -1090 -1090 -1090 -1090 -1090 -1090 -1090 -1090 -1090 -1090 -1090 -1090 -1090 -1090 -1090 -1090 -1090 -1090 -1090 -1090 -1090 -1090 -1090 -1090 -1090 -1090 -1090 -1090 -1090 -1090 -1090 -1090 -1090 -1090 -1090 -1090 -1090 -1090 -1090
102 DUMMY12 103 DUMMY13 104 DUMMY14 105 DUMMY15 106 DUMMY16 107 DUMMY17 108 DUMMY18 109 DUMMY19 110 DUMMY20 111 DUMMY21 112 DUMMY22 113 DUMMY23 114 DUMMY24 115 116 OSCVDD VREG
117 DUMMY25 118 FUSE1
119 DUMMY26 120 FUSE2
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(Unit: m) No. Name X 2944 3008 3072 3136 3200 3264 3328 3392 3456 3520 3584 3648 3712 3776 3840 3904 3968 4032 4096 4160 4224 4288 4352 4416 4480 4544 4608 4672 4753 4988 4988 4988 4988 4988 4988 4988 4988 4988 4988 4988 Y -1090 -1090 -1090 -1090 -1090 -1090 -1090 -1090 -1090 -1090 -1090 -1090 -1090 -1090 -1090 -1090 -1090 -1090 -1090 -1090 -1090 -1090 -1090 -1090 -1090 -1090 -1090 -1090 -1090 -1090 -1010 -950 -890 -830 -770 -710 -650 -590 -530 -470 No. 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 Name COM21 COM20 COM19 COM18 COM17 COM16 COM15 COM14 COM13 COM12 COM11 COM10 COM9 COM8 COM7 COM6 COM5 COM4 COM3 COM2 COM1 ICONA SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 SEG17 SEG18 X 4988 4988 4988 4988 4988 4988 4988 4988 4988 4988 4988 4988 4988 4988 4988 4988 4988 4988 4988 4988 4988 4988 4790 4710 4650 4590 4530 4470 4410 4350 4290 4230 4170 4110 4050 3990 3930 3870 3810 3750 Y -410 -350 -290 -230 -170 -110 -50 10 70 130 190 250 310 370 430 490 550 610 670 730 790 870 1083 1083 1083 1083 1083 1083 1083 1083 1083 1083 1083 1083 1083 1083 1083 1083 1083 1083 No. 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 Name SEG19 SEG20 SEG21 SEG22 SEG23 SEG24 SEG25 SEG26 SEG27 SEG28 SEG29 SEG30 SEG31 SEG32 SEG33 SEG34 SEG35 SEG36 SEG37 SEG38 SEG39 SEG40 SEG41 SEG42 SEG43 SEG44 SEG45 SEG46 SEG47 SEG48 SEG49 SEG50 SEG51 SEG52 SEG53 SEG54 SEG55 SEG56 SEG57 SEG58 X 3690 3630 3570 3510 3450 3390 3330 3270 3210 3150 3090 3030 2970 2910 2850 2790 2730 2670 2610 2550 2490 2430 2370 2310 2250 2190 2130 2070 2010 1950 1890 1830 1770 1710 1650 1590 1530 1470 1410 1350 Y 1083 1083 1083 1083 1083 1083 1083 1083 1083 1083 1083 1083 1083 1083 1083 1083 1083 1083 1083 1083 1083 1083 1083 1083 1083 1083 1083 1083 1083 1083 1083 1083 1083 1083 1083 1083 1083 1083 1083 1083
121 DUMMY27 122 FUSE3
123 DUMMY28 124 FUSE4
125 DUMMY29 126 FUSE5
127 DUMMY30 128 FUSE6
129 DUMMY31 130 FUSE7
131 DUMMY32 132 FUSE8
133 DUMMY33 134 FUSE9
135 DUMMY34 136 FUSE10
137 DUMMY35 138 FUSE11
139 DUMMY36 140 FUSE12
141 DUMMY37 142 FUSE13
143 DUMMY38 144 FUSE14
145 DUMMY39 146 147 FUSE15 FUSE16
148 DUMMY40 149 150 151 152 153 154 155 156 157 158 159 160 FUSE17 COM32 COM31 COM30 COM29 COM28 COM27 COM26 COM25 COM24 COM23 COM22
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(Unit: m) No. 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 Name SEG59 SEG60 SEG61 SEG62 SEG63 SEG64 SEG65 SEG66 SEG67 SEG68 SEG69 SEG70 SEG71 SEG72 SEG73 SEG74 SEG75 SEG76 SEG77 SEG78 SEG79 SEG80 SEG81 SEG82 SEG83 SEG84 SEG85 SEG86 SEG87 SEG88 SEG89 SEG90 SEG91 SEG92 SEG93 SEG94 SEG95 SEG96 SEG97 SEG98 X 1290 1230 1170 1110 1050 990 930 870 810 750 690 630 570 510 450 390 330 270 210 150 90 30 -30 -90 -150 -210 -270 -330 -390 -450 -510 -570 -630 -690 -750 -810 -870 -930 -990 -1050 Y 1083 1083 1083 1083 1083 1083 1083 1083 1083 1083 1083 1083 1083 1083 1083 1083 1083 1083 1083 1083 1083 1083 1083 1083 1083 1083 1083 1083 1083 1083 1083 1083 1083 1083 1083 1083 1083 1083 1083 1083 No. 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 Name SEG99 SEG100 SEG101 SEG102 SEG103 SEG104 SEG105 SEG106 SEG107 SEG108 SEG109 SEG110 SEG111 SEG112 SEG113 SEG114 SEG115 SEG116 SEG117 SEG118 SEG119 SEG120 SEG121 SEG122 SEG123 SEG124 SEG125 SEG126 SEG127 SEG128 SEG129 SEG130 SEG131 SEG132 SEG133 SEG134 SEG135 SEG136 SEG137 SEG138 X -1110 -1170 -1230 -1290 -1350 -1410 -1470 -1530 -1590 -1650 -1710 -1770 -1830 -1890 -1950 -2010 -2070 -2130 -2190 -2250 -2310 -2370 -2430 -2490 -2550 -2610 -2670 -2730 -2790 -2850 -2910 -2970 -3030 -3090 -3150 -3210 -3270 -3330 -3390 -3450 Y 1083 1083 1083 1083 1083 1083 1083 1083 1083 1083 1083 1083 1083 1083 1083 1083 1083 1083 1083 1083 1083 1083 1083 1083 1083 1083 1083 1083 1083 1083 1083 1083 1083 1083 1083 1083 1083 1083 1083 1083 No. 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 338 339 340 341 342 343 344 345 346 347 348 349 350 351 352 353 354 355 356 357 358 359 360 Name SEG139 SEG140 SEG141 SEG142 SEG143 SEG144 SEG145 SEG146 SEG147 SEG148 SEG149 SEG150 SEG151 SEG152 SEG153 SEG154 SEG155 SEG156 SEG157 SEG158 SEG159 SEG160 COM33 COM34 COM35 COM36 COM37 COM38 COM39 COM40 COM41 COM42 COM43 COM44 COM45 COM46 COM47 COM48 COM49 COM50 X -3510 -3570 -3630 -3690 -3750 -3810 -3870 -3930 -3990 -4050 -4110 -4170 -4230 -4290 -4350 -4410 -4470 -4530 -4590 -4650 -4710 -4790 -4988 -4988 -4988 -4988 -4988 -4988 -4988 -4988 -4988 -4988 -4988 -4988 -4988 -4988 -4988 -4988 -4988 -4988 Y 1083 1083 1083 1083 1083 1083 1083 1083 1083 1083 1083 1083 1083 1083 1083 1083 1083 1083 1083 1083 1083 1083 870 790 730 670 610 550 490 430 370 310 250 190 130 70 10 -50 -110 -170
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(Unit: m) No. 361 362 363 364 365 366 367 368 369 370 371 372 Name COM51 COM52 COM53 COM54 COM55 COM56 COM57 COM58 COM59 COM60 COM61 COM62 X -4988 -4988 -4988 -4988 -4988 -4988 -4988 -4988 -4988 -4988 -4988 -4988 Y -230 -290 -350 -410 -470 -530 -590 -650 -710 -770 -830 -890 No. 373 374 375 376 377 378 379 380 381 382 383 384 Name COM63 COM64 ICONB TEST1 TEST2 TEST3 TEST4 TEST5 TEST6 TEST7 TEST8 TEST9 X -4988 -4988 -4988 3575 3575 3575 3575 3575 3575 3575 3575 3575 Y -950 -1010 -1090 -573 -473 -373 -261 -161 -61 39 139 239 No. 385 386 387 388 389 390 391 392 393 394 Name TEST10 TEST11 TEST12 TEST13 TEST14 TEST15 TEST16 TEST17 TEST18 TEST19 X 3575 3575 3795 3795 3795 3795 3795 3795 3795 3795 Y 339 439 -573 -473 -261 -161 -61 139 239 339
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Pin Function
Pin Name SEG1~160 COM1~64 ICON DB0~DB5 DB6 (SCK) DB7 (SI) RS Pin No. I/O Output Output Output I/O LCD drive segment signals LCD drive common signals LCD drive common signal (used for icon) Data bus When P/S = low, DB0 to DB5 are placed in the high-impedance state. Data bus When P/S = low, this bus functions as the serial interface's data synchronizing clock (SCK). Data bus When P/S = low, this bus functions as the serial interface's data input pin (SI). Register mode select signal When RS = low, this input is recognized as a register number. When RS = high, this input is recognized as the data to be written to the register. Read select signal When 68/80 = low (80-series MPU selected), data is output while this pin is held low. Data is latched in at the active edge. When 68/80 = high (68-series MPU selected), this pin is used as an enable signal input pin (E). Write select signal When 68/80 = low (80-series MPU selected), data is latched at the rising edge of /WR. When 68/80 = high (68-series MPU selected), data read is selected if R/W = high or data write is selected if R/W = low. Chip select signal (1) Data/commands can be input or output while this signal is held low. Chip select signal (2) Data/commands can be input or output while this signal is held high. Reset signal The device is reset when this signal is pulled low. Parallel/serial interface select signal The parallel interface is selected when this signal is high. The serial interface is selected when this signal is low. 68/80-series parallel MPU select signal The 68-series parallel MPU is selected when this signal is high. The 80-series parallel MPU is selected when this signal is low. CR oscillator circuit ON/OFF select signal The internal CR oscillator is turned on when CLS is high. The internal CR oscillator is turned off when CLS is low, allowing for an external clock input to be used. In this case, use the CL pin to supply the external clock. Display clock input pin When CLS = high, this pin functions as the internal CR circuit's clock monitor pin. When CLS = low, this pin is used to input an external clock to the device. Standby signal The device is placed in standby state when / STB is low. External capacitor connecting pin for x2 step-up x2 step-up voltage output pin External capacitor connecting pin for x3 step-up x3 step-up voltage output pin External capacitor connecting pin for x4 step-up x4 step-up voltage output pin External capacitor connecting pin for x5 step-up x5 step-up voltage output pin LV regulator output pin LCD drive power supply pin (Note 1) (Note 1) Function
I/O
I/O
Input
/RD (E)
Input
/WR (R/W)
Input
/CS1 CS2 /RST
Input Input Input
P/S
Input
68/80
Input
CLS
Input
CL
I/O
/STB C1A, C1B VOUT1 C2A, C2B VOUT2 C3A, C3B VOUT3 C4A, C4B VOUT4 VREG VCC
Input
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Pin Name VLC0 to VLC4 VLC5 OSCVDD AVDD, AVSS DVDD, DVSS FUSE1 to 17 TEST1 to 19 Pin No. I/O LCD drive power supply pin LCD drive power supply pin: Connect to VSS CR oscillator circuit regulator output pin: Leave this pin open. Analog circuit power supply pin Digital circuit power supply pin LSI Test pins: Leave these pins open. LSI Test pins: Leave these pins open. Function (Note 1)

(Note 1): Connect the capacitor between this pin and VSS.
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Function Each Block
MPU interface unit
Depending on whether the 68/80 input and P/S input pins are high or low, the T6K11 selects an 8-bit parallel or a serial interface, allowing for data to be transferred from the MPU.
P/S 68/80 Interface Type 80-series MPU ( /CS1) 80-series MPU (CS2) 68-series MPU Serial /CS1 /CS1 L L L CS2 H CS2 H H RS RS RS RS RS /WR /WR /WR R/W H/L /RD /RD /RD E H/L DB7 DB7 DB7 DB7 SI DB6 DB6 DB6 DB6 SCK DB5 to 0 DB5 to 0 DB5 to 0 DB5 to 0 Hi-Z
H
L
H L
Note: "H" denotes the DVDD level; "L" denotes the DVSS level.
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(a) For the 80-series MPU
(b) For the 68-series MPU
(c) For serial interface
Fig. 1
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When the serial interface is selected (P / S = low), data and serial clock from the MPU are accepted providing that / CS1 = low and CS2 = high. The serial data input to the device is taken in from SI in order of DB7, DB6, xxxDB0 at each rising edge of SCK, and are converted into parallel data at the 8th rising edge of SCK. Recognition of the received data depends on the RS pin status at the 8th rising edge of SCK. If RS = low, the data is recognized as a register number set; if RS = high, the data is recognized as write data. A serial interface timing chart is shown in Fig. 2. Note that when using the serial interface, the device can only write data to its internal logic and registers, and cannot read data and status.
Fig. 2
Input / output buffer
This buffer is used to transfer data between the T6K11 and the MPU. For a parallel interface, this buffer is used as an 8-bit data bus ; for a serial interface, it is used to receive serial data and serial clock, with the serial data converted into parallel data before being taken into the internal circuit.
Input register
This register holds the data from the MPU. The data held in this register is recognized as a register number or write data depending on whether RS is high or low.
Output register
This register holds 8-bit data when transferring display RAM data or status information to the MPU.
X-address counter
This counter is a 64-Up / Down counter used to hold the row address of the display RAM. When this counter is selected by a command, it is automatically incremented or decremented each time data is read or written to the display RAM.
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Y-address counter
This counter is a 20-Up / Down counter used to hold the column address of the display RAM. When this counter is selected by a command, it is automatically increased or decreased each time data is read or written to the display RAM.
Z counter
This counter is a 64-Up counter used to supply the display data stored in the display RAM to the LCD drive circuit. The data held in the Z-address register is loaded into this counter as Z-address. Therefore, if this counter is set to 20, for example, it counts up from 20 to 21, 22, xxx62, 63, (icon) and from 0 to 1, 2, xxx18, 19, 20. The start line on the LCD screen is line 20 of the display RAM. Note, however, that the icon line (64) cannot be made the start line of the Z-address.
X / Y counter up / down register
This register holds the data that selects the up-count or down-count mode for the X and Y counters.
X / Y counter select register
This register holds the data that selects the X or Y counter to be used.
Display ON / OFF register
This 1-bit register holds the data that determines whether the display be turned on or off. When turned OFF, outputs from the display RAM are reset. When turned ON, the display data corresponding to those in the display RAM are output to the LCD. Since the data in the display RAM does not affect display ON/OFF command control, the display RAM is not cleared anyway.
Z-address register
This 6-bit register holds the data that determines the display start line. By setting Z-address in this register successively, it is possible to scroll the display up or down.
Oscillator
The clocking source can be switched between the built-in CR oscillator or an external clock depending on the CLS pin status as shown in Fig. 3. When CLS = high, the CR oscillator is enabled, supplying display clock to the internal logic. When CLS = low, the CL pin is switched for input, accepting an external clock.
Fig. 3
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Timing signal generation circuit
This circuit generates the timing signals and operation clock required for display by dividing the clock frequency derived from the CR circuit or an external source.
Shift registers
The T6K11 contains a 64-bit shift register necessary to shift the turn-on data required for the LCD drive common signals and a 1-bit shift register used for the icon.
Duty cycle control register
This register holds the data that sets one of the four duty cycles that can be used.
Contrast control register
This register holds 4-stage VLC0 control data and 64-stage contrast control data.
Step-up circuit ON / OFF register
This register holds the data that determines whether the step-up circuit be turned on or off.
D / A converter ON / OFF register
This register holds the data that determines whether the D/A converter be turned on or off.
Bias control register
This register holds the data that sets one of the four bias values that can be used.
Latch circuit
This circuit latches display data from the RAM.
LCD drive circuit (segment)
The segment driver circuit consists of 160 drivers. Each driver outputs one of the four LCD drive voltage levels depending on a combination of the display data from the latch circuit and the M signal (used for FR) as shown in Fig. 4. The segment driver circuit is shown below.
Fig. 4
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LCD drive circuit (common)
The common driver circuit consists of 65 drivers. Each driver outputs one of the four LCD drive voltage levels depending on a combination of the data from the shift register and the M signal (used for FR) as shown in Fig. 5. The common driver circuit is shown below.
Fig. 5
Step-up circuit
The T6K11 contains a x2/3/4/5 step-up circuit. When / RST = low or / STB = low, VOUT = 0 V (VSS level). Normally, capacitors of more or less 2.2 F are used for the step-up capacitor and step-up level retaining capacitor. Since the step-up circuit power supply AVDD pin normally allows voltages to be input that are higher than possible for the digital-block power supply DVDD pin, this circuit can generate the necessary LCD drive voltage. However, because the rated LCD drive voltage is 16.5 V (max), care must be taken for the voltage condition (AVDD voltage) used in step-up circuit and the number of boost steps to ensure that the boosted voltage (the voltage output from VOUT) will not exceed the rated voltage of 16.5 V. Note 1: Relationship of power supply voltages .............. 5.5 V AVDD DVDD 2.4 V Note 2: Relationship between step-up output voltage and LCD drive voltage .............. 16.5 V AVDD x n ( `n' denotes the number of boost steps.) Example): When using a x5 step-up circuit
Fig. 6
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Recommended Pin Processing When using a Step-up Circuit
Conditions When using x2 step-up circuit When using x3 step-up circuit When using x4 step-up circuit When using x5 step-up circuit C1A, C1B Available Available Available Available VOUT1 Available Available Available Available C2A, C2B Open Available Available Available VOUT2 Open Available Open Open C3A, C3B Open Open Available Available VOUT3 Open Open Available Open C4A, C4B Open Open Open Available VOUT4 Open Open Open Available
Note: "Available" means that a capacitor is connected to the pin.
Contrast control, bias control, and D / A converter
The T6K11 contains a power supply generating circuit for LCD drive which is comprised of the D / A converter. The contrast (electronic VR) and bias required for each type of LCD panel are controlled by this circuit. Refer to Fig. 7 for a block diagram of this power supply circuit.
Fig. 7 Resistor Ratios for Adjusting LCD Drive Voltage (VLC0)
VLC0 Control DB7 DB6 1 1 0 0 1 0 1 0 VLC0 Voltage Typ. Value (Max Contrast) 14.0 V 13.0 V 12.0 V 11.0 V 64 Steps Number of Contrast Steps VCC Input Voltage Min Value 15.0 V 14.0 V 13.0 V 12.0 V Ta = 25C 1/9 bias Remark
(Note): The VLC0 voltage is derated with respect to temperature by 0%/C of centigrade in the range of minimum to maximum values. Therefore, voltage fluctuations due to temperature may be depicted like the one shown below.
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About display RAM area
The T6K11's display RAM has a row of 160 cells in the segment direction and a row of 65 cells in the common direction, together constituting 10, 400 bits of memory capacity. The relationship between the dot matrix LCD ( = display screen) and the display RAM is such that one dot on the display screen corresponds to one bit in the display RAM as shown in Fig. 8. If the data written to the display RAM is a logic 1, the corresponding dot on the display screen is turned on (black) ; if the data is a logic 0, the corresponding dot on the display screen is turned off (white). The relationship between display RAM and dot matrix LCD is shown below.
Fig. 8
Note that if a duty cycle other than 1 / 64 is selected and a Z-address other than ZAD = 00h is set, the effective display RAM area is moved. The table below shows the relationship between duty cycle and Z-address settings and the resulting RAM area.
Effective Ram Area Segment Common Direction Direction 160 lines 160 lines 160 lines 160 lines 35 lines 49 lines 55 lines 65 lines Range of XAD when Z-Address is set to 00h XAD = C0~E1h, 80h XAD = C0~EFh, 80h XAD = C0~F5h, 80h XAD = C0~FFh, 80h Range of XAD when Z-Address is set to 05h XAD = C5~E6h, 80h XAD = C5~F4h, 80h XAD = C5~FAh, 80h XAD = C5~C4h, 80h (Note 1)
Duty Setting 1 / 35 duty 1 / 49 duty 1 / 55 duty 1 / 65 duty
Remark
Note 1: Even when ZAD is set to any value other than 00h, the effective display RAM area is the full size, so that the range of XAD is the same as XAD = C0 to FFh and 80h shown above. Here, XADICON is expressed as 80h. For details about the specification of XADICON, refer to the command description (R4) on page 20. The Z-address is effective in the range of XAD0 to 63 and does not affect XADICON.
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Page Configuration of Display RAM
Fig. 9 Command Definition
Command Set Register (REG) Status Read (STRD) Display Mode (DPE) Counter Mode (CSE) Analog Control Mode (APE) Alternating Signal Mode (FRS) Set Y-address (SYE) Set X-address (SXE) Set Z-address (SZE) Contrast Control (SCE) Data Write (DAWR) Data Read (DARD) D/A Converter Power Control (OPC) Reg No. R0 R1 R2 R3 R4 R5 R6 RS 0 0 1 1 1 1 1 1 1 1 1 1 1 / WR 0 1 0 0 0 0 0 0 0 0 0 1 0 / RD 1 0 1 1 1 1 1 1 1 1 1 0 1 ON/ OFF * fCDA DB7 * * * * CDA * 0 1 * DB6 * * * * DC * * N/F * * DB5 * * * * * DB4 * * * * * DB3 DB2 DB1 DB0
Register (0 to 15) RST CDR * N/F X/Y U/D SDR * D/F DP
X/Y U/D DUTY (0 to 3)
BIAS (0 to 3)
FRS control (0 to 63) Y-address (0 to 19) X-address (0 to 63) Z-address (0 to 63) Contrast control (0 to 63)
VLC0 control
R7 R12
Write data Read data OC Bias Current Control (0 to 15)
Test Mode (TEST)
R8 to 11 R13 to 15
1
0
1
Test mode (Do not access these registers)
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Set register (REG)
RS 0 /WR 0 /RD 1 DB7 * DB6 * DB5 * DB4 * DB3 DB2 DB1 DB0
Register (0 to 15)
This command selects a register No. When data is input after executing this command, the data is written to the register.
R0: Display mode (DPE)
RS 1 /WR 0 /RD 1 DB7 * DB6 * DB5 * DB4 * DB3 CDR DB2 SDR DB1 N/F DB0 DP
This command sets a display mode. When data is input after executing this command, the contents shown below are set. CDR: Sets the common data scanning direction. CRD = 0 : Data is scanned in the direction ICON COM64 COM1. CRD = 1 : Data is scanned in the direction COM1 COM64 ICON. SDR: Sets the segment data direction. SDR = 0 : SEG1 SEG160 with respect to the data direction DB7 DB0 SDR = 1 : SEG1 SEG160 with respect to the data direction DB0 DB7 N/F: Selects between normal display and icon display modes. N/F = 0 : Icon display mode is selected. N/F = 1 : Normal display mode is selected. DP: Turns display ON or OFF. DP = 0 : Display is turned OFF. DP = 1 : Display is turned ON.
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R1: Counter mode (CSE)
RS 1 /WR 0 /RD 1 DB7 * DB6 * DB5 * DB4 * DB3 * DB2 * DB1 Y/X DB0 U/D
This command sets a counter mode. When data is input after executing this command, the contents shown below are set.
DB1 0 0 1 1 DB0 0 1 0 1 Y-counter/Down mode is selected. Y-counter/Up mode is selected. X-counter/Down mode is selected. X-counter/Up mode is selected
The X and Y counters count the X and Y addresses of the display RAM when reading or writing to the RAM. This command selects either X or Y counter and also determines whether the selected counter counts up or down. Only one of the four available modes can be selected.
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R2: Set analog control mode (APE)
RS 1 /WR 0 /RD 1 DB7 CDA DB6 DC DB5 * DB4 * DB3 DB2 DB1 DB0
BIAS (0 to 3)
DUTY (0 to 3)
This command selects analog control and sets bias and duty cycle. When data is input after executing this command, the contents shown below are set. CDA : Turns the D/A converter for the LCD drive power supply ON or OFF. CDA = 0 : The D/A converter is turned OFF. CDA = 1 : The D/A converter is turned ON. DC : Turns the step-up circuit on or off. DC = 0: The step-up circuit is turned OFF. DC = 1: The step-up circuit is turned ON. BIAS : Sets a power supply bias for the LCD drive.
DB3 0 0 1 1 DB2 0 1 0 1 Set to 1/6 bias. Set to 1/7 bias. Set to 1/8 bias. Set to 1/9 bias.
DUTY: Sets a display duty cycle.
DB1 0 0 1 1 DB0 0 1 0 1 Set to 1/35 duty. Set to 1/49 duty. Set to 1/57 duty. Set to 1/65 duty.
(Note): The T6K11s COM output which corresponds to the line of LCD is changed by the Duty. When CDR = 1, COM outputs in each Duty are shown below.
1/n duty 1/35 duty 1/49 duty 1/57 duty 1/65 duty LCD 1 line,
st
2
nd
line,................................................,
n line, ICON
th
COM1, COM2,.........,COM17, COM33, COM34,.........,COM49, ICON COM1, COM2,............,COM24, COM33, COM34,.........,COM56, ICON COM1, COM2,...............,COM28, COM33, COM34,.........,COM60, ICON COM1, COM2,..................,COM32, COM33, COM34,.........,COM64, ICON
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R3: Set alternating signal mode (APE)
RS 1 /WR 0 /RD 1 DB7 * DB6 * DB5 DB4 DB3 DB2 DB1 DB0
FRS CONTROL (0 to 63)
This command sets a number of lines at which the alternating signal (FR) should be inverted every time. When data is input after executing this command, the contents shown below are set. FRS = 0 : A 1/m (*1) duty is selected according to the DUTY that is set in the R2 register and the alternating signal (FR) is inverted at a number of lines equal to the selected duty cycle. FRS 0 : The alternating signal (FR) is inverted at a number of lines that equals the written data + 1. *1: This is one of 1/35 duty, 1/49 duty, 1/57 duty, or 1/65 duty.
R4: Set Y-address (SYE)
RS 1 /WR 0 /RD 1 DB7 0 DB6 * DB5 * DB4 DB3 DB2 DB1 DB0
Y-ADDRESS (0 to 19)
This command sets a Y-address which is comprised of 20 pages. One of these pages is selected as data is written to the display RAM. When reset, the Y-address is set to page 0.
Set X-address (SXE)
RS 1 /WR 0 /RD 1 DB7 1 DB6 N/F DB5 DB4 DB3 DB2 DB1 DB0
X-ADDRESS (0 to 63)
This command sets an X-address by selecting between display RAM and flag (icon) RAM. Address selection between display RAM and flag (icon) RAM is controlled by the data in DB7. When N/F = 1, the display RAM is selected. In this case, the low-order data (DB0 to DB5) are identified as X-address, and an X-address can be selected from addresses 0 through 63. When N/F = 0, the flag (icon) RAM address (64) is selected irrespective of the low-order data (DB0 to DB5). When reset, the X-address is set to address 0 in the display RAM.
R5: Set Z-address (SZE)
RS 1 /WR 0 /RD 1 DB7 * DB6 * DB5 DB4 DB3 DB2 DB1 DB0
Z-ADDRESS (0 to 63)
This command sets a Z-address. The display RAM and flag (icon) RAM are separated and only the display RAM is selected. By selecting any address in the column direction of the display RAM, it is possible to set the first line on the LCD screen. The display data can be scrolled in the vertical direction by setting the first line in this way. For example, if the Z-address is set to 20, the first line on the LCD screen corresponds to Z-address 20 in the display RAM, and the last line on the LCD screen corresponds to Z-address 19 in the display RAM. When reset, the Z-address is set to address 0.
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R6: Contrast control (SCE)
RS 1 /WR 0 /RD 1 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
VLC0 CONTROL
CONTRAST CONTROL (0 to 63)
This command sets VLC0 voltage adjustment resistance ratio and contrast control. These two controls adjust the density of display on the LCD screen. The density of display can be selected from 4 64 steps, where 00H is the lightest, and FFH the darkest. When reset, contrast control is set to 00H.
R7: Data write (DAWR) / data read (DARD)
RS 1 1 /WR 0 1 /RD 1 0 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
WRITE DATA READ DATA
These commands enable data write and read to and from the display RAM. This single command register R7 manages both data write and read to and from the display RAM. To write display data into the display RAM, set the X and Y addresses of the display RAM, then select this register (R7) and write the data to the selected addresses of the display RAM. To read data from the display RAM, set the X and Y addresses of the display RAM, then select this register (R7) and place it in the read mode ( / RD = 0).
R12: D/A converter power control (OPC)
RS 1 /WR 0 /RD 1 DB7 ON/OFF DB6 * DB5 fCDA DB4 OC DB3 DB2 DB1 DB0
BIAS CURRENT CONTROL (0 to 15)
This command selects D/A converter power control and sets bias current control. ON/OFF: Turns the power control circuit of the D/A converter ON or OFF. ON/OFF = 0 : The power control circuit is turned OFF. ON/OFF = 1 : The power control circuit is turned ON. When data is input after executing this command, the contents shown below are set. fCDA: Sets an operating frequency of the D/A converter. fCDA = 0 : Set to 1280 Hz. fCDA = 1 : Set to 640 Hz. OC: Turns the D/A converter offset voltage compensation circuit ON or OFF. OC = 0: The offset voltage compensation circuit is turned OFF. OC = 1 : The offset voltage compensation circuit is turned ON. Bias Current Control: This command controls the bias current of the D/A converter. This command selects one of 16 levels. When DB0 to DB3 are all 1, the bias current is set to maximum value. When DB0 to DB3 are all 0, the bias current is set to minimum value. When reset, this register contents are set to 94 H by default. fCDA = 0, OC = 1, Bias Current Control = 0100 (bin). If the power control circuit is turned OFF, the contents except ON/OFF (DB7) are initialized.
R8 to R15, R13 to R15: Test mode (TEST)
RS 1 /WR 0 /RD 1 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0
WRITE DATA
These command registers are provided for test. Do not choose these registers.
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Functional Description
About the X-address and Y-address counters
The following explains the operation of the X-address and Y-address counters in connection with each command. A typical operation of the X-address counter is shown in Fig. 10 After a reset, the X-address (XAD) is set to 0 and the X-counter / Up mode is selected by the command CSE. Next, the X-address is set to 62 by the command SXE. Then when data is read or written to the display RAM, the X-address counter is automatically incremented as it continues counting up. When data is read or written at XAD = 63, the X-address is recycled to 0. Now the X-address / Down mode is selected by the command CSE. Then when data is read or written to the display RAM, the X-address counter is automatically decremented as it continues counting down. When data is read or written at XAD = 0, the X-address is recycled to 63. The command CSE is effective for either X or Y counter selected. In the example here, the X-address counter is selected by CSE, so the Y-address counter does not count.
Fig. 10
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Fig. 11 shows a typical operation of the Y (page) -address counter. After a reset, the Y (page) -address (YAD) is set to 0 and the Y (page) -counter / Up mode is selected by the command CSE. Then when data is read or written to the display RAM, the Y (page) -address counter is incremented. When data is read or written at YAD = 19, the Y (page) -address is recycled to 0. Similarly, if the Y (page) Down mode is selected by the command CSE, the Y (page) -address is automatically decremented as the counter continues counting down. When data is read or written at YAD = 0, the Y (page) -address is recycled to 19. In the example here, the Y (page) -address counter is selected by CSE, so the X-address counter does not count.
Fig. 11
Data read
When executing Data Read, the T6K11 directly accesses the display RAM addresses to read out data. Therefore, when the Data Read command is executed after setting the X and Y addresses, data is output immediately from the display RAM.
Fig. 12
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FRS control
The T6K11 has a command FRS that allows you to choose a number of lines at which the alternating signal (FR) is inverted every time. The T6K11's alternating signal can be inverted in the range of two lines up to the same number of lines as the duty cycle. Normally, 00H may be selected for the FRS command, so that the FR signal is inverted when the same number of lines as the duty cycle are latched every time. To obtain better display quality, FRS need to be adjusted to match the characteristics of each type of LCD panel used.
(a) For 1 / 65 duty and FRS = 00H (inverted at 64 + 1 lines)
Fig. 13
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(b) For 1 / 35 and FRS = 10H (inverted at 16 + 1 lines)
Fig. 14
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Standby function
The T6K11 has a /STB pin. When input to this pin is pulled low, the T6K11 enters a standby state. In this state, the CR circuit clock driver is deactivated and the device is placed in a Low Power mode to suppress current consumption. Even when the T6K11 is in standby state (the CR circuit is deactivated, so is the LCD display clock), it can be communicated from the MPU. Since data read/write operations are possible while the display is turned off, this helps to reduce current consumption. In standby state, all of the LCD drive power supply pins VLC0 to VLC5 are tied to the VSS level. When the standby function is used, the data in the display RAM is the display data that has been stored in it before the standby function is turned on.
Function Normal state Standby state Oscillator Operable Deactivated LCD Drive Power Supply Operable Fixed to VSS level LCD Drive Output Operable Fixed to VSS level
Reset function
The T6K11 has a / RST pin. When input to this pin is pulled low, the T6K11 is reset, with its internal circuits (register contents) initialized as shown below. (1) Display direction (2) Display mode (3) Display (4) Counter ............... CDR = 1, SDR = 1 Normal display mode Turned OFF Y-counter, Up mode CDA = 0, DC = 0 1/9 bias 1/65 duty FRS = 00H (FR inverted at the same number of lines as the duty cycle) 00H (lightest)
...................
............................. ............................ ..................
(5) Analog control (6) Bias
.................................. ........................
(7) Duty cycle
(8) Alternating signal (FR) .......
(9) Contrast
...........................
The T6K11 does not have a facility to reset the display RAM (to clear the data in it). In the initial state (immediately after power-ON), the display RAM contains indeterminate data which are either high or low. Therefore, Toshiba recommends using the Data Write command to execute a display clearing sequence before reading or writing to the display RAM.
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Oscillation frequency
The T6K11 contains a CR oscillator. The T6K11's frame frequency (fFR) is derived from the CR circuit's oscillation frequency (fosc) by diving it an appropriate value. The relationship between the oscillation frequency (fosc) and the frame frequency (fFR) is shown below.
FRS Selection Inverted at duty Inverted at duty Inverted at duty Inverted at duty Inverted at 17 lines Inverted at 2 lines Oscillation Frequency (fosc) 41 kHz CL Frequency
fOSC 8 fOSC 10 fOSC 12 fOSC 16 fOSC 8 fOSC 256
Duty Cycle 1 / 65duty
fFR Frequency
fOSC 8 65 fOSC 10 57 fOSC 12 49 fOSC 16 35 fOSC 8 17 fOSC 256 2
1 / 57duty
41 kHz
1 / 49duty
41 kHz
1 / 35duty
41 kHz
1 / 65duty
41 kHz
1 / 2duty
41 kHz
Note: The T6K11 has its fFR frequency varied by the FRS setup data. Therefore, consider the relationship between the duty cycle and the number of inversion lines when you adjust the fFR frequency to suit he CD panel used.
The relationship between bias control and contrast control
The contrast adjustment range of VLC0 is varied according to the BIAS that is set in the R2 register and VLC0 CONTROL that is set in the R6 register. So, it is necessary to control these registers when you adjust the VLC0 output voltage to suit the LCD panel used. The relationship between the BIAS and the VLC0 output voltage is shown below.
R6: VLC0 control DB7 1 N/F = 1 1 0 0 1 N/F = 0 1 0 0 DB6 1 0 1 0 1 0 1 0 1/6 bias 9.33 8.67 8.00 7.34 3.33 3.25 3.15 3.04 VLC0 output voltage (V) 1/7 bias 10.89 10.11 9.33 8.56 3.89 3.79 3.67 3.55 1/8 bias 12.45 11.55 10.67 9.78 4.55 4.33 4.20 4.05 1/9 bias 14.00 13.00 12.00 11.00 5.00 4.87 4.72 1.56
Display mode
(Note): The VLC0 output voltage values are typical values at max contrast.
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LCD drive waveform
(a) For normal display mode where duty cycle = 1/65 and FRS = 00h
Fig. 15
(b) For power save mode where duty cycle = 1/2
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Maximum Ratings (Referenced to VSS = 0 V, Ta = 25C unless otherwise noted)
Characteristics Power Supply Voltage (1) Power Supply Voltage (2) Input Voltage (1) Input Voltage (2) Output Voltage (1) Output Voltage (2) Operating Temperature Storage Temperature Symbol DVDD, AVDD (Note 2) VINA VIND VOA VOD Topr Tstg Rating -0.3~VSS + 7.0 -0.3~VSS + 18.0 -0.3~AVDD + 0.3 -0.3~DVDD + 0.3 -0.3~VSS + 18.0 -0.3~DVDD + 0.3 -25~75 -40~125 Unit V V V V V V C C Remark (Note 1) (Note 1), (Note 3) (Note 1), (Note 4) (Note 1), (Note 4) (Note 1) (Note 1)
Note 1: Note 2: Note 3: Note 4: Note 5:
These values are referenced to AVSS = DVDD = 0 V. VCC, VLC0, VLC1, VLC2, VLC3, VLC4, VLC5 The condition VCC VLC0 VLC1 VLC2 VLC3 VLC4 VLC5 must always be met. The condition AVDD DVDD must always be met. If the device is used exceeding its absolute maximum ratings, the device may not only break down but also loose reliability and malfunction. Therefore, Toshiba recommends that for normal operation, the device be used within the range of electrical characteristics shown in the next page.
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Electrical Characteristics DC Characteristics (1) referenced to DVDD = 3.0 V, AVDD = 3.0 V, VSS = 0 V, VCC = 15.0 V,
VLC0 = 14.0 V, Ta = -20 to 60C unless otherwise noted
Characteristics Operating Voltage (1) Operating Voltage (2) Operating Voltage (3) High Level Low Level High Level Low Level Symbol AVDD DVDD VCC VCL0 VIH VIL VOH VOL Rcol1 Test Circuit Test Condition IOH = -400 A IOL = 400 A (Note 2) Min DVDD 1.8 6.0 - VSS 0.80 x DVDD 0 DVDD - 0.2 0 Typ. 3.0 3.0 Max 5.5 3.3 16.5 - VSS DVDD 0.20 x DVDD DVDD 0.2 7.5 Unit V V V V (Note 1) V V DB0 to DB7 V k SEG1 to SEG160 Relevant Pin AVDD DVDD VCC, VCL0
Input Voltage
Output Voltage
Normal Mode Segment Driver ON- Power Resistance Save Mode Normal Mode Common Driver ON- Power Resistance Save Mode Input Leakage Current Output Leakage Current
Rcol2
(Note 3)
15.0
k
Rrow1
(Note 2)
1.5
k
Rrow2
(Note 3)
5.0
k
COM1 to COM64 ICON
IIL IOL

VIND = DVDD to GND VOD = DVDD to GND
-1 -1

1 1
A A
(Note 1) DB0 to DB7
Note 1: This applies to pins DB0 through DB7, RS, /WR, /RD, /CS1, CS2, /RST, /STB, P/S, 68/80, and CLS. Note 2: Referenced to AVDD = 3.0 V, DVDD = 3.0 V, VLC0 = 11.0 V, VCC = 16.5 V, 1/9 bias, current load Iload = 100 A, Ta = 25C. Note 3: Referenced to AVDD = 3.0 V, DVDD = 3.0 V, VLC0 = 4.0 V, VCC = 6.0 V, 1/9 bias, current load Iload = 100 A, Ta = 25C.
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DC Characteristics (2) referenced to DVDD = 3.0 V, AVDD = 3.0 V, VSS = 0 V, VCC = 15.0 V,
VLC0 = 14.0 V, Ta = -20 to 60C unless otherwise noted
Characteristics Operating Frequency (Input Frequency) Output Frequency External Clock Frequency External Clock Duty Cycle External Clock Rise / Fall Time Symbol CLIN CLO Fex Fduty Tr / Tf Test Circuit Test Condition Min 39 39 45 Typ. 41 41 41 50 Max 43 43 55 10 Unit kHz kHz kHz % ns Relevant Pin CL CL CL CL CL
DC Characteristics (3) referenced to DVDD = 3.0 V, AVDD = 3.0 V, VSS = 0 V, Ta = -20 to 60C
unless otherwise noted
Characteristics Output Voltage Characteristic (Using x2 Step-up Circuit) Output Voltage Characteristic (Using x3 Step-up Circuit) Output Voltage Characteristic (Using x4 Step-up Circuit) Output Voltage Characteristic (Using x5 Step-up Circuit) Symbol Test Circuit (1) Test Condition Min Typ. Max Unit Relevant Pin
VO1
(Note 4)
5.50
5.60
V
VOUT1
VO2
(2)
(Note 5)
8.33
8.55
V
VOUT2
VO3
(3)
(Note 6)
11.25
11.50
V
VOUT3
VO4
(4)
(Note 7)
14.15
14.40
V
VOUT4
Note 4: Referenced to DVDD = AVDD = 3.0 V, Iload = 200 A, VCC = 6.0 V (supplied from external source), CnA - CnB = 1.0 F, VOUTn - VSS = 1.0 F, CL = 41.0 kHz. Note 5: Referenced to DVDD = AVDD = 3.0 V, Iload = 200 A, VCC = 9.0 V (supplied from external source), CnA - CnB = 1.0 F, VOUTn - VSS = 1.0 F, CL = 41.0 kHz. Note 6: Referenced to DVDD = AVDD = 3.0 V, Iload = 200 A, VCC = 12.0V (supplied from external source), CnA - CnB = 1.0 F, VOUTn - VSS = 1.0 F, CL = 41.0 kHz. Note 7: Referenced to DVDD = AVDD = 3.0 V, Iload = 200 A, VCC = 15.0 V (supplied from external source), CnA - CnB = 1.0 F, VOUTn - VSS = 1.0 F, CL = 41.0 kHz.
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DC Characteristics (4) referenced to DVDD = 3.0 V, AVDD = 3.0 V, VSS = 0 V, Ta = -20 to 60C unless otherwise noted
Characteristics Current Consumption (1) Current Consumption (2) Current Consumption (3) Current Consumption (4) Current Consumption (5) Symbol ISS1 ISS1 ISS3 ISS4 ISSSTB Test Circuit Test Condition (Note 8) (Note 9) (Note 10) (Note 11) (Note 12) Min Typ. 235 250 470 40 Max 315 360 500 45 1 Unit A A A A A Relevant Pin VSS VSS VSS VSS VSS
Note 8: Referenced to AVDD = DVDD = 3.0 V, AVSS = DVSS = 0 V, VCC = VOUT4 (using x 5 step-up), internal CR oscillator turned on (CL = 41 kHz), 1/9 bias, 1/65 duty, D/A converter turned on, LCD nonloaded, display pattern: all "white," no data access, normal display mode, contrast control: R5 = BFH, VLC0 = 13.0 V, Ta = 25C, FRS = 0H. Note 9: Referenced to AVDD = DVDD = 3.0 V, AVSS = DVSS = 0 V, VCC = VOUT4 (using x 5 step-up), internal CR oscillator turned on (CL = 41 kHz), 1/9 bias, 1/65 duty, D/A converter turned on, LCD nonloaded, display pattern: "checker," no data access, normal display mode, contrast control: R5 = BFH, VLC0 = 13.0 V, Ta = 25C, FRS = 0H. Note 10: Referenced to AVDD = DVDD = 3.0 V, AVSS = DVSS = 0 V, VCC = VOUT4 (using x 5 step-up), internal CR oscillator turned on (CL = 41 kHz), 1/9 bias, 1/65 duty, D/A converter turned on, LCD nonloaded, display pattern: "checker," data access performed ( /CE = 1 MHz), normal display mode, contrast control: R5 = BFH, VLC0 = 13.0 V, Ta = 25C, FRS = 0H. Note 11: Referenced to AVDD = DVDD = 3.0 V, AVSS = DVSS = 0 V, VCC = VOUT4 (using x 5 step-up), internal CR oscillator turned on (CL = 41 kHz), 1/9 bias, 1/2 duty, D/A converter turned on, LCD nonloaded, display pattern: "checker," no data access, power save mode. Note 12: Referenced to AVDD = DVDD = 3.0 V, AVSS = DVSS = 0 V, VCC = 16.5 V, LCD nonloaded, no data access.
unless otherwise noted
Characteristics
DC Characteristics (5) referenced to DVDD = 3.0 V, AVDD = 3.0 V, VSS = 0 V, Ta = 25C
Symbol Test Circuit VLC0 Output Voltage V0out VLC0 Output Voltage Inclination V0INC Test Condition Ta = 25C Ta = 25C Ta = 25C Ta = 25C Ta = -20 to 60C (Note 13) (Note 14) (Note 15) (Note 16) (Note 13) Min 13.8 12.8 11.8 10.8 -0.05 Typ. 14.0 13.0 12.0 11.0 V0out Max 14.2 13.2 12.2 11.2 0.05 Unit V V V V %/C Relevant Pin VLC0 VLC0 VLC0 VLC0 VLC0
Note 13: AVDD = DVDD = 3.0 V, AVSS = DVSS = 0 V, 1/65 duty, 1/9 bias, VCC = 15.0 V (supplied from external source), CONTRAST CONTROL (R5) = FFh, D/A converter turned on, LCD nonloaded, normal display mode. Note 14: AVDD = DVDD = 3.0 V, AVSS = DVSS = 0 V, 1/65 duty, 1/9 bias, VCC = 14.0 V (supplied from external source), CONTRAST CONTROL (R5) = BFh, D/A converter turned on, LCD nonloaded, normal display mode. Note 15: AVDD = DVDD = 3.0 V, AVSS = DVSS = 0 V, 1/65 duty, 1/9 bias, VCC = 13.0 V (supplied from external source), CONTRAST CONTROL (R5) = 7Fh, D/A converter turned on, LCD nonloaded, normal display mode. Note 16: AVDD = DVDD = 3.0 V, AVSS = DVSS = 0 V, 1/65 duty, 1/9 bias, VCC = 12.0 V (supplied from external source), CONTRAST CONTROL (R5) = 3Fh, D/A converter turned on, LCD nonloaded, normal display mode.
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DC Characteristics (6) referenced to DVDD = 3.0 V, AVDD = 3.0 V, VSS = 0 V, Ta = -20 to 60C unless otherwise noted
Characteristics D/A Converter Output Voltage Offset (1) D/A Converter Output Voltage Offset (2) D/A Converter Output Voltage Offset (3) Symbol Vopoff1 Vopoff2 Voffset1 Voffset2 Vopoffs Test Circuit Test Condition (Note 17, 21, 22) (Note 18, 21, 22) ILoad = 20 A ILoad = 3 A (Note 19, 21, 22) Min -200 -200 Typ. 50 30 Max 200 200 80 50 200 Unit mV mV mV mV mV Relevant Pin (Note 20) (Note 20) VLC0, VLC2, VLC3 VLC1, VLC4 (Note 20)

-200
Note 17: Referenced to AVDD = DVDD = 3.0 V, AVSS = DVSS = 0 V, 1/65 duty, 1/9 bias, VCC = 15.0 V (supplied from external source), contrast control = Max, D/A converter: ON, step-up circuit: OFF, LCD nonloaded, normal display mode. VLC0 pin: 14.0 - VLC0 = Vopoff1 VLC1 pin: (VLC0 x 8/9) - VLC1 = Vopoff1 VLC2 pin: (VLC0 x 7/9) - VLC2 = Vopoff1 VLC3 pin: (VLC0 x 2/9) - VLC3 = Vopoff1 VLC4 pin: (VLC0 x 1/9) - VLC4 = Vopoff1 Note 18: Referenced to AVDD = DVDD = 3.0 V, AVSS = DVSS = 0 V, 1/2 duty, 1/9 bias, VCC = 6.0 V (supplied from external source), contrast control = Max, D/A converter: ON, step-up circuit: OFF, LCD nonloaded, power save mode. VLC0 pin: 5.0 - VLC0 = Vopoff2 VLC1 pin: (VLC0 x 8/9) - VLC1 = Vopoff2 VLC2 pin: (VLC0 x 7/9) - VLC2 = Vopoff2 VLC3 pin: (VLC0 x 2/9) - VLC3 = Vopoff2 VLC4 pin: (VLC0 x 1/9) - VLC4 = Vopoff2 Note 19: Referenced to AVDD = DVDD = 3.0 V, AVSS = DVSS = 0 V, 1/65 duty, 1/9 bias, VCC = 15.0 V (supplied from external source), contrast control = Max, D/A converter: ON, step-up circuit: OFF, LCD nonloaded, normal display mode. Vopoffs = ((VLC1 - VLC2) - (VLC0 - VLC1)) + ((VLC3 - VLC4) - (VLC4 - VLC5)) Note 20: VLC0, VLC1, VLC2, VLC3 and VLC4. Note 21: VLC0, VLC2, VLC3: ILoad = 30 A Note 22: VLC1,VLC4: ILoad = 3 A
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Test Circuits
(1) Test circuit for cases when x2 step-up circuit is used
(2) Test circuit for cases when x3 step-up circuit is used
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(3) Test circuit for cases when x4 step-up circuit is used
(4) Test circuit for cases when x5 step-up circuit is used
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AC Characteristics (1)
80-series parallel interface read / write characteristics
Test Condition
Referenced to VSS = 0 V, DVDD = AVDD = 2.4 to 2.7 V, VCC = AVDD, Ta = -20 to 60C unless otherwise noted
Characteristics Enable Cycle Time Enable Pulse Width Enable Rise / Fall Time Address Setup Time Address Hold Time Data Setup Time Write Data Hold Time Data Delay Time Read Data Hold Time Symbol tcycE PWEL tEr, tEf tAS tAH tDS tDHW tDD tDHR Min 1000 500 25 25 130 70 50 Max 20 400 Unit ns ns ns ns ns ns ns ns ns
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Referenced to VSS = 0 V, DVDD = AVDD = 2.7 to 3.3 V, VCC = AVDD, Ta = -20 to 60C unless otherwise noted
Characteristics Enable Cycle Time Enable Pulse Width Enable Rise/Fall Time Address Setup Time Address Hold Time Data Setup Time Write Data Hold Time Data Delay Time Read Data Hold Time Symbol tcycE PWEL tEr, tEf tAS tAH tDS tDHW tDD tDHR Min 500 300 20 20 60 50 20 Max 15 200 Unit ns ns ns ns ns ns ns ns ns
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AC Characteristics (2)
68-series parallel interface read / write characteristics
Test Condition
Referenced to VSS = 0 V, DVDD = AVDD = 2.4 to 2.7 V, VCC = AVDD, Ta = -20 to 60C unless otherwise noted
Characteristics Enable Cycle Time Enable Pulse Width Enable Rise / Fall Time Address Setup Time Address Hold Time Data Setup Time Write Data Hold Time Data Delay Time Read Data Hold Time Symbol tcycE PWEL tEr, tEf tAS tAH tDS tDHW tDD tDHR Min 1000 500 25 25 130 70 50 Max 20 400 Unit ns ns ns ns ns ns ns ns ns
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Referenced to VSS = 0 V, VDD = 2.7 to 3.3 V, VCC = AVDD, Ta = -20 to 60C unless otherwise noted
Characteristics Enable Cycle Time Enable Pulse Width Enable Rise/Fall Time Address Setup Time Address Hold Time Data Setup Time Write Data Hold Time Data Delay Time Read Data Hold Time Symbol tcycE PWEL tEr, tEf tAS tAH tDS tDHW tDD tDHR Min 500 300 20 20 60 50 20 Max 15 200 Unit ns ns ns ns ns ns ns ns ns
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AC Characteristics (3)
Serial interface read / write characteristics
Test Condition
Referenced to VSS = 0 V, DVDD = AVDD = 2.4 to 2.7 V, VCC = AVDD, Ta = -20 to 60C unless otherwise noted
Characteristics Clock Cycle Time Clock Pulse Width Clock Rise/Fall Time CS Setup Time CS Hold Time Address Setup Time Address Hold Time Data Setup Time Data Hold Time Symbol tcycC PWCL, PWCH tCr, tCf tCSS tCSH tAS tAH tDS tDH Min 1000 500 300 300 300 300 250 Max 20 250 Unit ns ns ns ns ns ns ns ns ns
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Referenced to VSS = 0 V, DVDD = AVDD = 2.7 to 3.3 V, VCC = AVDD, Ta = -20 to 60C unless otherwise noted
Characteristics Clock Cycle Time Clock Pulse Width Clock Rise/Fall Time CS Setup Time CS Hold Time Address Setup Time Address Hold Time Data Setup Time Data Hold Time Symbol tcycC PWCL, PWCH tCr, tCf tCSS tCSH tAS tAH tDS tDH Min 400 150 250 250 250 250 150 Max 15 150 Unit ns ns ns ns ns ns ns ns ns
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Example of Application Circuit
T6K11 Internal CR oscillator used x5 step-up circuit used 8-bit parallel MPU interface used
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